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MC100LVEL59 3.3V ECL Triple 2:1 Multiplexer
Description
The MC100LVEL59 is a 3.3 V triple 2:1 multiplexer with differential outputs. The output data of the multiplexers can be controlled individually via the select inputs or as a group via the common select input. The flexible selection scheme makes the device useful for both data path and random logic applications.
Features
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* * * * * *
Individual or Common Select Controls 500 ps Typical Propagation Delays ESD Protection: >2 kV HBM The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V Internal Input Pulldown Resistors
SO-20 WB DW SUFFIX CASE 751D
* * Q Output will Default LOW with Inputs Open or at VEE * Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test * Moisture Sensitivity;
MARKING DIAGRAM*
20 100LVEL59 AWLYYWWG
*
* * Pb-Free Packages are Available*
Pb Pkg Level 1 Pb-Free Pkg Level 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V-O @ 0.125 in, Oxygen Index 28 to 34 Transistor Count = 182 devices
1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 4
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Publication Order Number: MC100LVEL59/D
MC100LVEL59
VCC 20 Q0 19 Q0 18 VCC 17 Q1 16 Q1 15 VCC 14 Q2 13 Q2 12 VEE 11
1
0
1
0
1
0
1
2
3 D0b
4
5
6 D1b
7
8
9
10
COM_SEL D0a
SEL0 D1a
SEL1 D2a
D2b SEL2
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View) Table 1. PIN DESCRIPTION
Pins D0a-D2a D0b-D2b SEL0-SEL2 COM_SEL Q0-Q2; Q0-Q2 VCC VEE Function ECL Input Data a ECL Input Data b ECL Individual Select Input ECL Common Select Input ECL Differential Outputs Positive Supply Negative Supply
Table 2. TRUTH TABLE
SEL H L Data a b
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Wave Solder 0 lfpm 500 lfpm Standard Board <2 to 3 sec @ 248C 20 SOIC 20 SOIC 20 SOIC Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 to 0 -8 to 0 6 to 0 -6 to 0 50 100 -40 to +85 -65 to +150 140 100 30 to 35 265 Unit V V V V mA mA C C C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC100LVEL59
Table 4. LVPECL DC CHARACTERISTICS VCC= 3.3 V; VEE= 0.0 V (Note 1)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 0.5 2215 1470 2135 1490 Min Typ 27 2295 1605 Max 32 2420 1745 2420 1825 150 0.5 2275 1490 2135 1490 Min 25C Typ 27 2345 1595 Max 32 2420 1680 2420 1825 150 0.5 2275 1490 2135 1490 Min 85C Typ 27 2345 1595 Max 32 2420 1680 2420 1825 150 Unit mA mV mV mV mV mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 2. Outputs are terminated through a 50 W resistor to VCC - 2.0 V.
Table 5. LVNECL DC CHARACTERISTICS VCC= 0.0 V; VEE= -3.3 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current 0.5 -1085 -1830 -1165 -1810 Min Typ 27 -1005 -1695 Max 32 -880 -1555 -880 -1475 150 0.5 -1025 -1810 -1165 -1810 Min 25C Typ 27 -955 -1705 Max 32 -880 -1620 -880 -1475 150 0.5 -1025 -1810 -1165 -1810 Min 85C Typ 27 -955 -1705 Max 32 -880 -1620 -880 -1475 150 Unit mA mV mV mV mV mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 4. Outputs are terminated through a 50 W resistor to VCC - 2.0 V.
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MC100LVEL59
Table 6. AC CHARACTERISTICS VCC= 3.3 V; VEE= 0.0 V or VCC= 0.0 V; VEE= -3.3 V (Note 5)
-40C Symbol fmax tPLH tPHL tskew tJITTER tr tf Characteristic Maximum Toggle Frequency Propagation Delay Output-Output Skew Cycle-to-Cycle Jitter Output Rise/Fall Times Q (20% - 80%) 200 DATA to Q/Q SEL to Q/Q COM_SEL to Q/Q Any Dn, Dm to Q TBD 540 200 340 340 340 Min Typ TBD 690 690 690 100 TBD 540 200 340 340 340 Max Min 25C Typ TBD 690 690 690 100 TBD 540 340 340 340 Max Min 85C Typ TBD 690 690 690 100 Max Unit GHz ps
ps ps ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. VEE can vary 0.3 V.
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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MC100LVEL59
ORDERING INFORMATION
Device MC100LVEL59DW MC100LVEL59DWG MC100LVEL59DWR2 MC100LVEL59DWR2G Package SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) Package 38 Units / Rail 38 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPS I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100LVEL59
PACKAGE DIMENSIONS
SO-20 WB DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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L
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MC100LVEL59/D

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